1. Field of the Invention
The present invention relates to pipeline ADC (analog-digital converter), in particular to pipeline ADC that uses minimum overhead in digitally correcting the errors in its internal comparators.
2. Description of Related Art
Pipeline ADCs are well known in prior. FIG. 1 depicts a typical N-stage pipeline ADC 1000 comprising a sample-and-hold amplifier SHA 100, N pipeline stages 200_1, 200_2, 200_3, and so on, and an output encoder 300. SHA 100 converts the continuous-time input voltage x(t) into discrete-time analog sample x0[n], which is the value of the input voltage x(t) at the time instant of nT, where T is the period of the sampling clock and n is a time index. The first stage 200_1 receives the analog sample x0[n] and generates two outputs: a digital output y1[n] that is a coarse digital representation of x0[n−1] (which is the analog sample of previous time step), and an analog output x1[n] that represents the residual error of the coarse quantization. The residual error is passed to its next stage (2nd stage 200_2) for further processing. In this manner, each pipeline stage, said stage k, receives an analog sample from its preceding stage, said stage (k−1), (except for the first stage, which does not have a preceding stage but receives the analog sample from SHA 100), generates a digital output which represents a coarse quantization of its input of the previous time step, and passes an analog output, which represented the residual error of the quantization, to its subsequent stage, said stage (k+1). For the last stage (Nth stage 200_N), there is no subsequent stage and therefore it does not need to generate the residual error. The digital outputs of all these pipeline stages are passed to an output encoder 300, which encodes them into a single output sequence y[n], which is the end result of the analog-to-digital conversion for the analog input voltage x(t).
FIG. 2 depicts a typical pipeline stage 200_k (k=1, 2, and so on). In accordance with the clock CLK, the analog input sample xk−1[n] is sampled and held by S/H 230. Also, the analog input sample xk−1[n] is converted into a digital output yk[n+1] by a Gk-level ADC (analog-digital converter) 210_k. (The time index n is increased by 1 to reflect one-clock latency between input and output.) Let the full-scale range of the input voltage be from −VREF to VREF. Without loss of generality, we may normalize the ADC levels so that a digital output “1” would correspond to the full-scale voltage VREF. At the clock edge when S/H 230 latches the input, ADC 210_k determines which one of its Gk levels is closest to the input. The ADC level that is closest to the input xk−1[n], denoted as yk[n+1], is the digital output of this stage of the next time index. The digital output is passed to a Gk-level DAC (digital-analog-converter) 220_k, which converts the digital output into analog voltage, resulting in a coarse representation of the analog input xk−1[n]. The coarse representation from DAC 220_k is subtracted from the analog input sample xk−1[n] via a summer 240. The output of summer 240 represents the quantization error due to the analog to digital conversion. The Gk levels of ADC 210_k (and also of DAC 220_k) are uniformly distributed between −VREF·(Gk−1)/Gk to VREF·(Gk−1)/Gk, inclusively, therefore the spacing between two adjacent levels is always 2·VREF/Gk. As a result, the quantization error is always between −VREF/Gk and VREF/Gk. A gain block 250_k is used to amplify the quantization error by a factor of Gk to boost it into the full-scale range of from −VREF to VREF. The resultant voltage, referred to as the “residual error” of this stage, is passed to the next stage for further processing. The gain block 250_k provides the so-called “inter-stage gain” so that full-scale range of each stage remains the same. For the last stage (Nth stage 200_N), there is an ADC 210_N for generating a digital output; there is no need to have S/H 230, DAC 220_N, summer 240, and gain block 250_N because there is no subsequent stage.
FIG. 3 depicts a typical output encoder 300. It receives digital outputs from all N pipeline stages, i.e. yk[n] for k=1 to N. The end result y[n] is obtained by summing up the digital outputs from all N pipeline stages. However, to account for the inherent pipeline delays associated with the pipeline stages, a series of unit-cycle delays 320_2, 320_3, and so on are needed when summing up the digital outputs from all N stages. Also, to account for the “inter-stage gain” we uses, a series of gain blocks 310_2, 310_3, and so on are needed to adjust the digital outputs from stages 2, 3, and so on. For stage 2, the output needs to be scaled by a factor of 1/G1 to offset the inter-stage gain provided by stage 1. For stage 3, the output needs to be scaled by a factor of 1/(G1 G2) to offset the inter-stage gains provided by stage 1 and stage 2. For stage k, the output needs to be scaled by a factor of 1/(G1 G2 . . . Gk−1) to offset the inter-stage gains provided by all its (k−1) preceding stages. Mathematically, the encoder output can be written as:y[n]=y1[n−(N−1)]+1/G1·y2[n−(N−2)]+1/(G1G2)·y3[n−(N−3)]+ . . . +1/(G1G2 . . . GN−2)·yN−1[n−1]+1/(G1G2 . . . GN−1)·yN[n]
Aforementioned prior art pipeline ADC is vulnerable to the error from Gk-level ADC 210_k of FIG. 2 due to the offsets in its internal comparators. To illustrate this problem, we may look at 2-level (1-bit) ADC for example. A 1-bit ADC has two levels: ½ and −½ (again, we normalize the full-voltage VREF to 1). It uses a comparator to compare the input with zero. If the input is greater than or equal to zero, the ADC determines that the level “½” best represents the input. Else, it determines that the level “−½” best represents the input.
Mathematically, the behavior of a 1-bit pipeline stage 200_k can be described as follows:
            y      k        ⁡          [              n        +        1            ]        =      {                                                                      1                /                2                                                                                                          x                                          k                      -                      1                                                        ⁡                                      [                    n                    ]                                                  ≥                0                                                                                                          -                  1                                /                2                                                                                      x                                      k                    -                    1                                                  <                0                                                    ⁢                                  ⁢                              x            k                    ⁡                      [                          n              +              1                        ]                              =              2        ·                  (                                                    x                                  k                  -                  1                                            ⁡                              [                n                ]                                      -                          VREF              ·                                                y                  k                                ⁡                                  [                                      n                    +                    1                                    ]                                                              )                    FIG. 4 depicts the ideal input-output transfer characteristics of pipeline stage 200_k of FIG. 2 using 2-level ADC-DAC with inter-stage gain of two (i.e. Gk=2). When the input xk−1[n] is positive or zero, the digital output is ½ and the analog output is 2·xk−1[n]−VREF; when the input xk−1[n] is negative, the digital output is −½ and the analog output is 2·xk−1[n]+VREF. However, the comparator within a practical ADC 210_k in the pipeline stage 200_k of FIG. 2 may likely have an offset so that it may make a wrong detection. For example, if there is an offset of VREF/8 in the comparator, the digital output will be ½ only when the input is greater than or equal to VREF/8. The input-output transfer characteristics for this particular instance is depicted in FIG. 5. For an input between 0 and VREF/8, the output will exceed the full scale of its next stage, resulting in significant error. Therefore, the comparator needs to be very accurate. Usually, the offset of the comparator needs to be smaller than the LSB (least significant bit) of the overall ADC. This requirement is usually very hard to fulfill.
To resolve this problem, prior art pipeline ADC usually employs a 3-level (1.5-bit) pipeline stage. A 1.5-bit stage is different from a 1-bit stage in using an additional level that best represents a small input. For example, besides the two decisions, “½” and “−½,” a 1.5-bit stage adds a 3rd level “0” when the input is between −VREF/4 and VREF/4. Mathematically, we have
            y      k        ⁡          [              n        +        1            ]        =      {                                                                      1                /                2                                                                                                          x                                          k                      -                      1                                                        ⁡                                      [                    n                    ]                                                  ≥                                  VREF                  /                  4                                                                                        0                                                                        x                                      k                    -                    1                                                  ≤                                                      x                                          k                      -                      1                                                        ⁡                                      [                    n                    ]                                                  <                                  VREF                  /                  4                                                                                                                          -                  1                                /                2                                                                                                          x                                          k                      -                      1                                                        ⁡                                      [                    n                    ]                                                  <                                                      -                    VREF                                    /                  4                                                                    ⁢                                  ⁢                              x            k                    ⁡                      [                          n              +              1                        ]                              =              2        ·                  (                                                    x                                  k                  -                  1                                            ⁡                              [                n                ]                                      -                          VREF              ·                                                y                  k                                ⁡                                  [                                      n                    +                    1                                    ]                                                              )                    
The ideal transfer function of a 1.5-bit pipeline stage is depicted in FIG. 6. Unlike 1-bit pipeline stage, 1.5-bit pipeline stage can tolerate a large offset in its internal comparators. The input-output transfer characteristics of a 1.5-bit pipeline stage with a comparator offset of VREF/8 is depicted in FIG. 7. Due to the extra “0” decision, the output will not exceed the full scale of its next stage even when the ADC makes a wrong decision. Although ADC makes wrong decisions due to comparator offset, the error due to the wrong decision is absorbed as part of the residual error of this pipeline stage. When the next stage takes the residual error for further processing, the error due to wrong decision in the preceding stage will be corrected because the error has been absorbed as part of its input. For example, consider the first two stages. Let the analog input be 5/16·VREF. If there is no comparator offset, the 1st stage generates a digital output ½ and a residual error −⅜·VREF. The 2nd stage takes the residual error from the 1st stage and generates a digital output −½ and a residual error ¼·VREF. The output encoder will then have the following representation for the input 5/16·VREF:(½)+2−1·(−½)=½−¼=¼
On the other hand, if the 1st stage has a comparator offset of VREF/8 while the 2nd stage does not, the 1st stage generates a wrong digital output 0 and a residual error ⅝·VREF. The 2nd stage takes the residual error from the 1st stage and generates a digital output ½ and a residual error ¼·VREF. The output encoder will then have the following representation for the input 5/16·VREF:0+2−1·(½)=0+¼=¼
It is clear that the error in the 1st stage (a wrong decision of “0) is corrected by the 2nd stage (an extra residual voltage of ⅝·VREF−(−⅜·VREF)=VREF). This is because the error due to the wrong decision from the 1st stage has been absorbed as part of the residual error and passed to the 2nd stage. Likewise if there is comparator error in the 2nd stage, it can be corrected by the 3rd stage. In this manner, the comparator error of any stage of interest can be corrected by its subsequent stage. This technique is commonly referred to as “digital error correction” for comparator error.
A 1.5-bit pipeline architecture greatly relaxes the requirement on the accuracy of the internal ADC of a pipeline stage, and therefore is a very popular architecture. Note that the maximum comparator offset that a 1.5-bit stage can tolerate is VREF/4. If the comparator offset is over VREF/4, the residual error can still exceed the full-scale range (from −VREF to VREF) and thus go beyond what can be corrected by the next stage. However, the overhead in allowing such a relaxation is quite high. A 1-bit pipeline stage only needs one comparator, while a 1.5-bit pipeline stage needs two comparators: one compares the input with VREF/4, the other with −VREF/4. The overhead in the number of comparators is 100%. Also, a 1-bit pipeline stage only needs a two-level DAC, while a 1.5-bits pipeline stage needs a three-level DAC. The overhead in DAC levels is 50%. As will become obvious later in this disclosure, this is nonetheless the best one can do for a pipeline stage with inter-stage gain of 2 (i.e. Gk=2). However, for inter-stage that is higher than 2, one can certainly do better than that.
Although in theory the inter-stage gain Gk can be any integer that is greater than 1, in practice people use exclusively powers of two (i.e. 2, 4, 8, 16, and so on) for easier signal processing in the output encoder. The top-level architecture of the prior art N-stage pipeline ADC with digital error correction is the same as that without digital error correction as depicted in FIG. 1 except for the following. Without digital error correction, the pipeline stages 200_1, 200_2, and so on, of FIG. 1 are implemented using the architecture 200_k depicted in FIG. 2; with digital error correction, these pipeline stages need to be replaced by pipeline stages 200A_1, 200A_2, and so on, respectively, which are implemented using the architecture 200A_k as depicted in FIG. 8. The architecture 200A_k depicted in FIG. 8 uses (2·Gk−1)-level ADC 210A_k and DAC 220A_k, while the architecture 200_k depicted in FIG. 2 uses Gk-level ADC 210_k and DAC 220_k. Digital error correction is implemented by simply changing Gk-level ADC-DAC to (2·Gk−1)-level ADC-DAC.
In prior art digital error correction scheme, the (2·Gk−1) levels (normalized with the full scale voltage VREF) for ADC-DAC are:
−(Gk−1)/Gk, −(Gk−2)/Gk, −(Gk−3)/Gk, . . . , −2/Gk, −1/Gk, 0, 1/Gk, 1/Gk, . . . , (Gk−3)/Gk, (Gk−2)/Gk, (Gk−1)/Gk 
For example, for inter-stage gain of 4, Paul C. Yu used 7-level stages with inter-stage gain of 4 in his article “A 14b 40 Msamples/s Pipelined ADC with DFCA” and the 7 levels are:
−¾, −½, −¼, 0, ¼, ½, ¾
Therefore, the overhead in ADC-DAC levels are (7−4)/4=75%.
For inter-stage gain of 8, Sang-Min Yoo et al. used 15-level stages with inter-stage gain of 8 in his article “A 2.5-V 10-b 120-MSamples/s CMOS Pipelined ADC Based on Merged-Capacitor Switching” and the 15 levels are:
−⅞, −¾, −⅝, −½, −⅜, −¼, −⅛, 0, ⅛, ¼, ⅜, ½, ⅝, ¾, ⅞
Therefore, the overhead in ADC-DAC levels are (15−8)/8=87.5%.
As will be shown later in this disclosure, one can certainly have much lower overhead in implementing digital error correction for these two cases.
What is needed is pipeline ADC that employs a digital error correction with minimum overhead in extra hardware.